Job Information
Google ASIC Design Lead, Machine Learning, Silicon in Bengaluru, India
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
10 years of experience in RTL design.
Experience leading a team completing the full development cycle of SoC subsystems (e.g., Neural Processing Units, GPU, DSP, or processors, from conception to production).
Experience working cross-functionally with Software, Architecture, Design Verification, and SoC integration teams.
Preferred qualifications:
Master's degree or PhD in Computer Science, Electrical Engineering, or a related field.
Experience in engineering across architecture, micro-architecture, design verification, implementation, emulation, and silicon bring-up.
Experience working with Design Verification and integration teams on methodologies that improve team productivity.
Experience with high performance compute IPs (e.g., GPUs, DSPs, or Neural Processing Units).
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.
Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.
Manage a team of RTL engineers, plan and lead the design of complex machine learning compute IPs by fully understanding the architecture specification, and interact with software and architecture engineers to identify important design requirements.
Engage with Verification and Silicon Validation teams to ensure functionality of the design.
Provide input on synthesis, timing closure, and physical design of digital blocks.
Participate, guide, and motivate the team for timely execution and exceptional Power Performance Area (PPA) benchmarks for these IPs that will go into a wide range of SoCs.
Work with SoC Design and other cross-functional implementation teams to make sure the IP design is successfully implemented through the downstream domains all the way to tape-out.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCPEEOPost.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.