Job Information
Microsoft Corporation Hardware Engineer II - Design Verification in Redmond, Washington
Microsoft Azure is building the fastest network in public cloud. We are seeking candidates who can span the stack from hardware to systems to applications, turning ideas into production systems at a rapid pace. Join us as a Hardware Engineer II - Design Verification
to build the world's fastest public cloud and make a difference to millions of people across the planet. We are looking for a Hardware Engineer II - Design Verification to work in the Accelnet Hardware team. You will be part of the design verification team, driving several features, developing and enhancing verification environment framework for software defined networking (SDN) accelerators in Azure Boost.
You will develop the infrastructure for next-generation SDN accelerators which can do arbitrary packet manipulations, provide network security, enhance connection establishment performance, and improve performance with Remote Direct Memory Access (RDMA) and custom network protocols. You should be able to drive projects with both hardware and software teams, both inside and outside of Microsoft.
Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
Responsibilities
Build scalable constrained random verification environment in system Verilog using prevalent verification methodologies.
Create comprehensive test plans to address functional scenarios in discussions with the software and hardware design teams.
Execute the test plan by adding testcases and tracking verification through coverage driven metrices.
Create and enhance verification environment by adding sequences, constraints, assertions, and functional coverage.
Scripts to automate and maintain execution of test suits to support continuous integration (CI) and continuous development (CD) flow.
Apply Agile development methodologies such as hosting code reviews, sprint planning, frequent deployment to cloud, and iterative development of features.
Handle occasional on-call responsibilities for addressing hardware issues reported by our customers.
Embody ourCulture (https://www.microsoft.com/en-us/about/corporate-values) andValues (https://careers.microsoft.com/us/en/culture)
Qualifications
Required Qualifications:
Bachelor's Degree in Computer Science or related technical field AND 2+ years technical engineering experience with coding in languages including, but not limited to, C, C++, C#, Java, JavaScript, or Python
OR equivalent experience.
Other Requirements:
- Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Additional / Preferred Qualifcations:
5+ years technical experience in hardware design verification, verification methodologies, and system Verilog.
OR Bachelor's Degree in Electrical Engineering, Computer Science, Computer Engineering, Information Technology, or related field AND 2+ years technical experience in network design, development, and automation.
OR Master's Degree in Electrical Engineering, Computer Science, Information Technology, or related field AND 1+ years technical experience in network design, development, and automation
OR Doctorate Degree in Electrical Engineering, Computer Science, Computer Engineering, Information Technology, or related field.
Understanding of constrained random verification principles and experience in writing comprehensive test plans.
7+ years of project experience verifying several designs at unit and system level.
Deep understanding of system Verilog constraints, functional coverage, and assertions.
Familiarity with formal verification.
Programming skills in C/C++, System Verilog, Assembly, and knowledge of advanced computer architecture.
Communication skills, team player, self-driven and problem-solving ability.
Experience in scripting languages such as Python and PowerShell.
Knowledge of networking fundamentals, including protocols such as IPV4, IPV6, TCP, UDP, DTLS, VXLAN, NVGRE, ICMP, ARP, among others.
Software Engineering IC3 - The typical base pay range for this role across the U.S. is USD $98,300 - $193,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $127,200 - $208,800 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay
Microsoft will accept applications for the role until June 28, 2024
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Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (https://careers.microsoft.com/v2/global/en/accessibility.html) .